The 2024 TSMC Technology Forum is an important technological event, during which TSMC announced a series of innovative achievements including the latest process technology, advanced packaging technology, and 3D integrated circuit (3D IC) technology.
TSMC unveiled its process technology called TSMC A16 (1.6nm) for the first time at the forum.
Summary of performance indicators for TSMC A16 (1.6nm) technology:
1. Process technology: TSMC A16 adopts a 1.6 nanometer process technology, which is currently one of the leading process technologies in the industry, aiming to provide higher performance and lower power consumption.
2. Super Rail Technology: This technology moves the power supply network from the back of the wafer, releasing more layout space for the signal network on the front of the wafer, thereby improving logic density and performance. This design makes A16 particularly suitable for high-performance computing (HPC) products with complex signal wiring and dense power supply networks.
3. Performance and power consumption: Compared with the N2P process, TSMC A16 increases speed by 8-10% at the same operating voltage (Vdd). At the same speed, its power consumption is reduced by 15-20%. This means that A16 can more effectively control power consumption while maintaining high performance, thereby extending the device's battery life and reducing heat dissipation issues.
4. Chip density: The chip density of TSMC A16 has increased by up to 1.10 times compared to the N2P process. This means that within the same physical space, A16 can accommodate more transistors and other electronic components, further enhancing its performance and computing power.
2024 TSMC Technology Forum, Eight Major Technologies:
TSMC A16 and TSMC's innovative NanoFlex technology support nanochip transistors, N4C technology, CoWoS, system integrated chips, as well as system level wafers (TSMC SoW), silicon photon integration, and advanced packaging for automotive applications.
TSMC A16: This is TSMC's first publicly disclosed process technology, which uses a 1.6 nanometer process, combined with a super rail architecture and nanosheet transistors, and is expected to be mass-produced in 2026. Compared to the N2P process, the A16 chip density has increased by up to 1.10 times, with a speed increase of 8-10% and a power consumption reduction of 15-20% under the same operating voltage.
NanoFlex technology: This is a technology paired with TSMC's upcoming N2 process, providing flexible standard components for chip designers. Components with lower heights can save area and have higher power efficiency, while components with higher heights maximize efficiency. Customers can optimize the combination of high and low components in the same design block, adjust the design to achieve the best balance between power consumption, efficiency, and area of the application.
N4C technology: This is the result of TSMC continuing N4P technology and is expected to be mass-produced in 2025. The grain cost can be reduced by up to 8.5% and the adoption threshold is low, which helps to provide cost-effective choices for products that emphasize value.
CoWoS technology: This is an advanced packaging technology that seamlessly integrates advanced processing units such as GPUs and artificial intelligence accelerators with high bandwidth memory (HBM) modules, reducing interconnect latency between homogeneous or heterogeneous logic SoCs and HBMs. This technology helps to improve the reliability, lifespan, and power integrity of the system, while reducing size and cost.
System Integrated Chip (TSMC SoIC): This is an innovative wafer level packaging technology that can integrate multiple small chips into a smaller and thinner system single chip. This technology can achieve heterogeneous 3D integrated circuits with high speed, high bandwidth, low power consumption, high spacing density, and minimal space occupation.
System level wafer (TSMC SoW): TSMC's first mass-produced SoW product adopts integrated fanout (InFO) technology primarily based on logic chips. The chip stacking version using CoWoS technology is expected to be ready by 2027, capable of integrating SoICs, HBMs, and other components to create a powerful wafer level system with computing power comparable to data center server racks or even entire servers.
Silicon Photon Integration: TSMC is developing Compact Universal Photon Engine (COUPE) technology, which uses SoIC-X chip stacking technology to stack electronic wafers on top of photonic wafers. Compared to traditional stacking methods, it can provide the lowest electrical resistance and higher energy efficiency for the interface between the two.
Advanced Packaging for Vehicles: Following the launch of the N3AE process to support automotive customers, TSMC is integrating advanced chips and packaging to meet their demand for higher computing power, while also complying with automotive safety and quality requirements.